ASIC Digital Design Senior/Staff Engineer

Job Title

ASIC Digital Design Senior/Staff Engineer

Role Summary

Lead RTL design and delivery of automotive digital IP (high-speed controllers such as PCIe, DDR, UCIe) intended for ISO 26262 ASIL D systems. Work across design, safety qualification, verification coordination, and synthesis/QoR to deliver production-quality IP.

Experience Level

Senior-level. Expect candidates with substantial industry experience (typically 6–8+ years of relevant ASIC/automotive IP experience).

Responsibilities

Accountable for RTL ownership, safety qualification, and mentoring within a digital IP team.

• Design and own synthesizable RTL for automotive IP blocks (PCIe, DDR, UCIe).
• Lead RTL coding, lint cleanup, CDC analysis, synthesis optimization, and debug.
• Coordinate with verification teams to define VIP scope, close coverage gaps, and validate controllers before tapeout.
• Drive safety qualification activities including DFMEA, FMEDA, and DFA to support ASIL D targets.
• Mentor and guide engineers on coding standards, design flows, and best practices for Verilog/SystemVerilog.
• Evaluate and apply design automation and AI-driven design tools to improve quality and reduce cycle time.

Requirements

Required technical skills and domain experience. Years-of-experience and degree details are listed under Education Requirements.

• Proven IP-level experience with high-speed interface protocols (PCIe, DDR, UCIe) and delivering production RTL.
• Practical knowledge and hands-on experience with ISO 26262 functional safety processes for hardware (DFMEA, FMEDA, DFA) up to ASIL D.
• Strong RTL expertise in synthesizable Verilog and SystemVerilog.
• Deep familiarity with ASIC design flows: lint, CDC, synthesis, static timing analysis, and formal verification.
• Demonstrated ability to lead individual-contributor design work while mentoring and guiding engineering teams.
• Experience applying design automation; scripting and use of AI-driven design tools is a plus.
• Ability to debug complex corner cases and close gaps between design intent and verification coverage.

Education Requirements

Bachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience working on Automotive SoCs or digital IP. Degree fields typically include Electrical/Electronic Engineering, Computer Engineering, Computer Science, or another related technical discipline; equivalent practical experience in ASIC/digital IP development is acceptable if it meets the stated experience levels.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.