ASIC Digital Design Senior Staff Engineer

Job Title

ASIC Digital Design Senior Staff Engineer

Role Summary

Lead verification ownership for critical IP subsystems within Synopsys' Noida engineering organization, driving verification strategy, execution, and signoff for complex multi-interface ASIC designs.

This role combines hands-on testbench development and debug with technical leadership and mentoring of a distributed verification team supporting AI accelerator, automotive SoC, and data center IP.

Experience Level

Senior — requires substantial experience; the posting indicates 10+ years of hands-on ASIC or FPGA verification experience.

Responsibilities

Primary responsibilities include defining verification strategy, building robust testbenches, and delivering signoff-quality IP.

• Lead verification for critical IP subsystems and coordinate execution across Noida and global sites.
• Architect and evolve subsystem-level UVM testbenches in SystemVerilog, integrating RTL, behavioral models, and protocol checkers.
• Develop advanced test scenarios, assertions, and checkers for corner cases across interfaces such as DDR, HBM, PCIe, UCIe, Ethernet, or UALink.
• Define verification test plans with coverage goals; track functional and code coverage and drive closure to signoff.
• Manage regression suites, perform root-cause analysis, and resolve simulation failures before they impact downstream teams.
• Collaborate with RTL designers and architects to clarify specifications and ensure correctness from design start.
• Mentor verification engineers on UVM methodology, debugging, and verification best practices; review code and PRs.

Requirements

Must-have technical skills and demonstrated leadership in verification delivery.

• 10+ years of hands-on ASIC/FPGA verification experience, with proven technical leadership in delivering IP to signoff.
• Deep expertise in UVM-based testbench architecture and SystemVerilog; ability to build new environments, not only maintain them.
• Experience with at least two of these protocols: DDR, HBM, PCIe, UCIe, Ethernet, UALink; ability to write protocol checkers and interface monitors.
• Proven ability to write complex assertions and functional coverage models and to debug large integrated testbenches.
• Ownership of end-to-end verification deliverables: planning, regression management, metrics tracking, and signoff.
• Hands-on experience extracting and acting on verification metrics using industry-standard coverage tools and methodologies.
• Strong debugging skills and willingness to be hands-on during regressions and off-hours when necessary.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Computer Science (the posting specifies these degrees). No explicit mention of acceptable equivalent experience beyond the stated years of verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.