ASIC Digital Design Principal Engineer

Job Title

ASIC Digital Design Principal Engineer

Role Summary

Lead micro-architecture and RTL design for high-speed memory and communication IP used in high-performance computing and data-center systems. Work on mixed-discipline teams to define, implement, and validate blocks intended for tapeout in advanced process nodes.

The role includes technical leadership, cross-functional coordination with analog, verification and physical-design teams, and mentoring of junior engineers.

Experience Level

Senior - requires 10+ years of hands-on ASIC digital design experience, with production tapeout history.

Responsibilities

Primary responsibilities include micro-architecture, RTL development, and ensuring designs meet performance, power, area and timing targets.

• Define micro-architecture for mixed-signal IP from specifications, balancing performance, power, area, latency and timing for HPC applications.
• Develop RTL for complex digital blocks in high-speed communication IP (DDR, HBM, or similar).
• Model circuit behavior to enable digital/analog co-design and early validation.
• Define and refine synthesis constraints and collaborate with physical design and timing-closure teams.
• Perform and review code-quality checks (linting, CDC and RDC analysis) and resolve violations early.
• Evaluate design trade-offs and recommend solutions aligned with product goals and market requirements.
• Mentor engineers: review designs, provide technical guidance, and develop team judgment and skills.

Requirements

Must-have technical skills and experience.

• 10+ years of hands-on ASIC digital design with a track record of taped-out silicon.
• Deep expertise with high-speed memory/communication protocols (DDR, HBM, or similar).
• Strong understanding of low-power design techniques applied in performance-critical contexts.
• Proven experience with clock-domain crossing (CDC) and reset-domain crossing (RDC) analysis and remediation.
• Experience with synthesis flows, physical-aware synthesis, and constraint definition for timing closure.
• Ability to collaborate effectively with circuit designers and verification/physical-design teams.
• Demonstrated mentorship and technical leadership skills.
• Familiarity with mixed-signal design environments is a plus.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field is requested. (No explicit mention of equivalent-experience language in the posting.)

Team and Benefits

Part of a multi-discipline product team building next-generation IP for HPC and AI infrastructure; work spans digital design, mixed-signal integration, verification and physical implementation.

Comprehensive health, wellness, and financial benefits are offered.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.