ASIC Digital Design Principal Engineer

Job Title

ASIC Digital Design Principal Engineer

Role Summary

Lead architecture and implementation of high-performance RTL IP cores for die-to-die communication protocols (for example UCIe) targeting automotive and consumer SoCs. Own design from micro-architecture through RTL, synthesis, timing closure, and customer integration while mentoring a distributed ASIC team.

Collaborate across Noida, Bangalore, and San Jose teams and with customer engineering groups to deliver production-ready IP.

Experience Level

Senior — requires 12+ years of hands-on ASIC digital design and RTL implementation experience.

Responsibilities

Own architecture, implementation, delivery, and team technical leadership for complex IP cores:

• Architect micro-architectures and produce implementable design specifications.
• Implement RTL in Verilog/SystemVerilog and drive synthesis, CDC analysis, formal checks, and static timing closure.
• Collaborate with verification to define test plans, close coverage gaps, and debug corner cases.
• Work with customers to clarify specifications and ensure integration readiness.
• Mentor and review the work of ASIC designers across multiple sites; establish design standards and best practices.
• Automate flows and manage revision control (Perforce); develop scripts in Perl or Shell as needed.

Requirements

Must-have technical skills and experience:

• Deep expertise in at least one protocol: UCIe, Ethernet, DDR, PCIe, CXL, or USB, with experience delivering designs to silicon or customers.
• Strong micro-architecture definition skills and RTL coding in Verilog/SystemVerilog.
• Practical experience with ASIC design flows: synthesis, CDC analysis, formal verification, and static timing analysis; familiarity with P&R-aware synthesis tools (e.g., Fusion Compiler) or equivalent.
• Proficiency with Perforce and scripting for automation (Perl, Shell).
• Proven experience technically leading and mentoring ASIC design teams.
• Nice-to-have: familiarity with IP reuse methodologies, IP quality processes, and multi-site/customer-facing verification collaboration.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE). The posting specifies 12+ years of hands-on ASIC digital design and RTL implementation experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.