ASIC Digital Design Manager
SynopsysJob Title
ASIC Digital Design Manager
Role Summary
Lead a team designing Ethernet MAC and PCS IP from microarchitecture through customer release. Manage technical direction, delivery, and cross-functional coordination to produce production-quality RTL for high-speed interfaces.
This role sits in the Synopsys Ethernet IP Group in Bengaluru and focuses on core IP development for networking applications.
Experience Level
Senior - requires 10+ years of ASIC digital design experience and 3+ years in a technical leadership or engineering management role.
Responsibilities
Accountable for technical leadership, team growth, and on-time delivery of Ethernet controller IP.
- Lead a team of digital design engineers through microarchitecture, RTL implementation, and customer release.
- Drive architectural and microarchitectural decisions and translate customer requirements into SystemVerilog implementations.
- Oversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across projects.
- Manage resource allocation, project execution, and collaboration with verification, physical design, and product teams.
- Conduct technical interviews and build a high-performing team through hiring and onboarding.
- Mentor engineers on high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies.
- Own performance reviews, career development planning, and succession planning for the team.
Requirements
Must-have technical skills and proven leadership experience.
- 10+ years hands-on ASIC digital design experience with emphasis on RTL development and microarchitecture.
- 3+ years in a technical leadership or engineering management role with demonstrated ability to mentor and grow teams.
- Expert-level proficiency in SystemVerilog and Verilog for synthesis and a track record of delivering production-quality RTL.
- Deep knowledge of high-speed interfaces/protocols such as Ethernet, PCIe, DDR, or AMBA (AXI/AHB/APB).
- Strong understanding of static timing analysis, synthesis, timing closure, and making microarchitectural tradeoffs for timing and power.
- Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies.
- Nice-to-have: experience with low-power design techniques (UPF), multi-voltage domain architectures, advanced process nodes (7nm/5nm), or hardware emulation platforms.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
