ASIC Digital Design Engineer

Job Title

ASIC Digital Design Engineer

Role Summary

Work on verification of high-speed interconnect IP (UCIe, PCIe, DDR) as part of the Synopsys IP Verification team in Hyderabad. Responsible for creating verification plans, building UVM testbenches, executing regressions, and driving coverage closure and first-silicon readiness.

Experience Level

Entry-level / Early-career - typically 2+ years of ASIC/SoC verification experience.

Responsibilities

Primary duties include planning, developing, and executing verification for protocol IP blocks and supporting tape-out readiness.

• Own verification planning and execution for UCIe, PCIe, or DDR IP blocks; translate protocol specifications into test plans, checkers, and SVA.
• Design and extend UVM testbenches: agents, sequencers, scoreboards, factories, and coverage models.
• Write constrained-random and directed SystemVerilog tests; run regressions and close functional and code coverage using VCS/Xcelium/Questa and URG.
• Perform root-cause analysis on RTL bugs, protocol compliance failures, and testbench issues using Synopsys Verdi.
• Mentor junior verification engineers, review test plans and coverage reports, and document verification results and debug findings.
• Contribute to regression infrastructure, coverage-closure strategies, and first-silicon readiness activities.

Requirements

Key technical skills and experience required; education details are under Education Requirements below.

• 2+ years of hands-on ASIC or SoC verification experience with ownership of IP block or subsystem-level verification.
• Strong working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, including link training, state machines, and compliance requirements.
• Solid UVM methodology experience and SystemVerilog for agents, sequencers, scoreboards, coverage models, and constrained-random stimulus.
• Proven debug skills using Synopsys Verdi for waveform, transaction-level, and protocol debug.
• Experience with industry simulators such as VCS, Xcelium, or Questa and familiarity with regression and coverage tools (e.g., URG).
• Nice-to-have: direct experience verifying UCIe PHY, PCIe controllers, or DDR memory controllers; VIP integration or formal verification experience.

Education Requirements

B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or a related technical discipline (as stated). Related technical degrees accepted.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.