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ASIC Digital Design Architect

Synopsys
July 29, 2026
Full-time
Remote friendly (Markham, Ontario, Canada)
Canada
$165,000 - $248,000 CAD yearly
RTL Design Jobs, Level - Senior

Job Title

ASIC Digital Design Architect

Role Summary

Senior digital architect responsible for designing digital subsystems for high-speed SerDes IP and mixed-signal interfaces (Ethernet, PCIe, SATA, USB). The role works across specification, RTL architecture, synthesis/timing closure, DFT, verification collaboration, and silicon bring-up.

Position is posted for Markham, ON and is open to candidates across Canada; the role can be hybrid or fully remote depending on location and preference.

Experience Level

Senior β€” typically 10+ years of hands-on digital ASIC design experience.

Responsibilities

Design and delivery responsibilities for digital portions of mixed-signal SerDes IP and related PHYs.

  • Architect and implement digital subsystems for high-speed SerDes IP (Backplane Ethernet, PCIe, SATA, USB).
  • Translate system-level requirements into RTL, design constraints, and interface specifications.
  • Define design flow decisions for CDC, synthesis, DFT insertion, and low-power architecture.
  • Collaborate with verification to create testplans, assertions, and coverage strategies; debug failures including gate-level sims.
  • Analyze timing and power, perform gate-level simulation and failure analysis across digital/analog boundaries.
  • Mentor and coach junior engineers on RTL quality, synthesis impact, and cross-functional collaboration.
  • Work with implementation and customer support teams to resolve issues and support silicon bring-up.

Requirements

Core technical skills and practical experience required for the role.

  • 10+ years of hands-on digital ASIC design experience in high-speed or mixed-signal environments.
  • Proficiency in Verilog or VHDL for RTL design and gate-level simulation.
  • Deep expertise in clock domain crossing design, analysis, and verification methodologies.
  • Experience with synthesis tools and techniques, timing closure, and power optimization.
  • Solid knowledge of DFT methodologies, including scan insertion, ATPG, and boundary scan.
  • Experience collaborating with verification teams on testplans, coverage closure, and failure analysis.
  • Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB (strong plus).

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. The posting accepts equivalent practical experience in lieu of the degree.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-07-27