ASIC DFT Technical Leader

Job Title

ASIC DFT Technical Leader

Role Summary

Senior technical lead in Cisco's Common Hardware Group (CHG) working on Silicon One networking ASIC development. The role drives design-for-test (DFT) strategy and implementation across front-end RTL, back-end physical design, and post-silicon validation to ensure testability and quality of complex networking chips.

Experience Level

Senior-level. The role expects at least 10 years of relevant industry experience in DFT, test, and silicon engineering.

Responsibilities

Primary responsibilities include leading DFT activities across the implementation flow and into post-silicon validation.

• Define and drive DFT requirements early in the design cycle with RTL and physical design teams.
• Design and integrate scan, JTAG, BIST (including memory BIST) and boundary-scan architectures.
• Lead ATPG flows and manage EDA test tool usage and flows (e.g., TestMax, Tetramax, Tessent).
• Support gate-level simulation, debugging, and signoff activities with simulators such as VCS.
• Coordinate post-silicon validation and debug, including ATE pattern work and P1687 usage.
• Drive DFT and quality processes across teams and mentor engineers on test architecture and methodology.

Requirements

Must-have technical skills and experience for this role.

• Extensive, recent hands-on experience in DFT, test, and silicon engineering (10+ years).
• Practical experience with JTAG protocols, scan architectures, BIST, and boundary scan.
• Experience with ATPG and test tools such as TestMax, Tetramax, Tessent, and familiarity with PrimeTime.
• Gate-level simulation and debugging experience with VCS or equivalent simulators.
• Post-silicon validation and ATE pattern experience; knowledge of P1687.
• Experience collaborating with front-end RTL and back-end physical design teams on DFT and signoff activities.
• Proven ability to lead technical processes and cross-functional design/test coordination.

Nice-to-have:

• Verilog design experience for custom DFT logic and IP integration.
• DFT CAD development experience (architecture, methodology, and infrastructure).
• Test static timing analysis and SystemVerilog equivalency checking skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required; the posting specifies at least 10 years of related experience. (No certifications specified.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).