ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join Cisco's Common Hardware Group within the Silicon One development organization as an ASIC engineer focused on Design-for-Test (DFT). The role partners with front-end RTL and backend physical design teams to define and integrate DFT requirements early in the design cycle and to support implementation and post-silicon validation.

Work includes developing DFT IP, enabling ATE/in-system test and debug, and contributing to testability and physical-design signoff for advanced silicon (bare die and stacked-die) platforms.

Experience Level

Mid-level — requires professional experience; the position expects candidates with approximately 5+ years of relevant ASIC/DFT experience.

Responsibilities

Primary responsibilities center on implementing and integrating DFT features across the full chip design and validation flow.

• Define and implement DFT features to support ATE, in-system test, debug and diagnostics.
• Develop reusable DFT IP and integrate testability features in RTL and full-chip integration.
• Collaborate with front-end design, verification, and physical design teams to enable integration and validation of test logic during implementation and post-silicon phases.
• Participate in DFT and physical-design strategy for new silicon device models, including bare die and stacked-die.
• Lead debugging and solution development with minimal mentorship during silicon bring-up and validation.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proven experience in DFT, test, and silicon engineering (industry experience with modern DFT practices).
• Practical knowledge of JTAG protocols, scan architectures, boundary scan, and memory BIST.
• Experience with ATPG and EDA tool flows such as TestMax/Tetramax/Tessent and PrimeTime.
• Gate-level simulation and debug experience using tools like VCS or equivalent simulators.
• Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Ability to design and integrate custom DFT logic and DFT IP into complex chip designs.

Nice-to-have:

• Verilog design experience and familiarity with functional verification.
• Test static timing analysis and SystemVerilog equivalency/logic checking skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies at least 5 years of relevant experience. No certifications were specified.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).