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ASIC DFT Engineer

Cisco Systems
July 21, 2026
Full-time
On-site
Austin, Texas, United States
$165,000 - $241,400 USD yearly
DFT Jobs, Level - Senior

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group to design and integrate Design-for-Test (DFT) solutions for high-performance networking ASICs. The role partners with front-end RTL, back-end physical design, verification, and validation teams to define and deliver testability features across implementation and post-silicon phases.

Experience Level

Senior β€” minimum 7 years of relevant DFT, test, or silicon engineering experience.

Responsibilities

Primary responsibilities include specifying, delivering, and validating DFT features and flows across design and silicon phases.

  • Implement hardware DFT features to support ATE, in-system test, debug and diagnostics.
  • Develop and integrate DFT IP and test logic in RTL and full-chip contexts.
  • Collaborate with design, verification, and physical design teams to enable test logic integration and validation during implementation and post-silicon flows.
  • Drive DFT and quality processes through implementation signoff, gate-level validation, and post-silicon debug.
  • Contribute to DFT and physical design strategies for new device models (bare die, stacked die) and reusable test/debug methodologies.
  • Debug complex test and silicon issues with minimal supervision.

Requirements

Key technical skills and tools required or preferred.

  • Must-have: 7+ years of experience in DFT, test, or silicon engineering; prior work with JTAG, scan, BIST (including memory BIST and boundary scan).
  • Must-have: Experience with ATPG and industry EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • Must-have: Gate-level simulation and debugging experience (e.g., VCS); post-silicon validation and ATE pattern experience, familiarity with P1687.
  • Nice-to-have: Verilog design experience for custom DFT logic and IP integration; familiarity with functional verification.
  • Nice-to-have: DFT CAD development experience (test architecture, methodology, infrastructure) and test static timing analysis.
  • Nice-to-have: SystemVerilog logic equivalency checking and test-timing validation skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required. The posting specifies a minimum of 7 years of related experience.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-07-21