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ASIC DFT Engineer

Cisco Systems
July 13, 2026
Full-time
On-site
Austin, Texas, United States
$165,000 - $241,400 USD yearly
DFT Jobs, Level - Senior

Job Title

ASIC DFT Engineer

Role Summary

As an ASIC DFT Engineer in Cisco's Silicon One development organization (Common Hardware Group), you will define and implement design-for-test features across RTL, physical design, implementation, and post-silicon validation phases. You will collaborate with front-end RTL, backend physical design, verification, and test teams to enable ATE, in-system test, debug, and diagnostics for high-performance networking ASICs.

Work on next-generation networking chips used in Cisco switching, routing, and wireless products.

Experience Level

Senior β€” requires 7+ years of relevant experience.

Responsibilities

Key responsibilities include:

  • Define and implement DFT features to support ATE, in-system test, debug, and diagnostics.
  • Develop DFT IP and integrate test logic with RTL and full-chip design flows.
  • Collaborate with design, verification, and physical design teams to validate test logic during implementation and post-silicon phases.
  • Contribute to DFT and physical design strategies for bare die, stacked die, and reusable test/debug approaches.
  • Lead debugging and problem resolution through implementation and silicon bring-up with minimal mentorship.

Requirements

Must-have skills and experience:

  • Proven experience in DFT, test, and silicon engineering (7+ years expected; degree details in Education Requirements).
  • Hands-on experience with JTAG, scan, and BIST architectures (including memory BIST and boundary scan).
  • Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • Gate-level simulation and debugging experience with VCS or similar simulators.
  • Post-silicon validation and debug experience, including working with ATE patterns and P1687.
  • Ability to design and troubleshoot DFT solutions independently.
  • Nice-to-have: DFT CAD development, Test Static Timing Analysis, Verilog/SystemVerilog for custom DFT logic and IP integration, SystemVerilog equivalency checking, and validating test timing.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required; minimum 7 years of relevant experience. No certifications specified in the posting.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-07-13