ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

The ASIC DFT Engineer will design, integrate, and validate Design-for-Test (DFT) features for high-performance networking ASICs in the Silicon One organization. The role works across front-end RTL, back-end physical design, and post-silicon validation teams to ensure testability, ATE support, and diagnostics throughout the implementation and silicon bring-up flows.

Experience Level

Senior level — role requires substantial hands-on experience in DFT and silicon engineering. Specific years of experience are listed under Education Requirements.

Responsibilities

Primary responsibilities include defining and delivering DFT functionality across chip development and validation phases.

• Specify and implement DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop DFT IP and integrate testability features into RTL and full-chip designs.
• Collaborate with front-end design, verification, and physical design teams to enable test logic integration during implementation and signoff.
• Drive post-silicon validation and debug efforts, including ATE pattern support and test infrastructure.
• Contribute to DFT and physical-design strategies for new device models (bare die, stacked die) and reusable test/debug approaches.
• Provide technical leadership to craft solutions and debug complex issues with minimal mentorship.

Requirements

Required technical skills and domain experience (education details are in Education Requirements below).

• Hands-on experience with DFT methodologies: JTAG, scan, BIST architectures (including memory BIST and boundary scan).
• Experience with ATPG and EDA tool flows (examples: TestMax, Tetramax, Tessent tool sets, PrimeTime).
• Gate-level simulation and debug experience using tools such as VCS or equivalent simulators.
• Post-silicon validation and debug experience, including ATE patterns and IEEE P1687 (or similar) usage.
• Ability to collaborate across RTL, verification, and physical design teams to integrate and validate test logic.
• Strong debugging skills and ability to deliver solutions with limited supervision.
• Preferred: Verilog/SystemVerilog design experience for custom DFT logic and IP integration; familiarity with functional verification flows.
• Preferred: DFT CAD development, test architecture/methodology, test static timing analysis, and SystemVerilog logic equivalency validation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required. The posting specifies at least 7 years of relevant industry experience in DFT, test, or silicon engineering. No certifications were specified.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).