ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

The ASIC DFT Engineer will define and implement design-for-test (DFT) features for high-performance networking ASICs within the Silicon One development organization. The role partners with front-end RTL teams, backend physical design teams, verification, and post-silicon validation to ensure testability, debug, and diagnostics across implementation and production.

Experience Level

Senior — requires at least 7 years of relevant DFT/test/silicon engineering experience.

Responsibilities

Primary responsibilities include design, integration, and validation of DFT features throughout the chip development lifecycle.

• Implement Hardware DFT features to support ATE, in-system test, debug and on-field diagnostics.
• Develop and integrate DFT IP in collaboration with RTL and multi-functional teams; drive full-chip testability integration.
• Work with front-end design, verification, and physical design teams to enable and validate test logic during implementation and post-silicon phases.
• Lead DFT activities for new device models (bare die, stacked die) and develop reusable test and debug strategies.
• Support post-silicon validation, debug, and ATE pattern development and execution.
• Drive DFT and quality processes through implementation flow and post-silicon validation with minimal supervision.

Requirements

Must-have technical skills and experience are listed first; preferred skills follow.

• Must-have: 7+ years of experience in DFT, test, and silicon engineering.
• Must-have: Experience with JTAG protocols, scan chains, BIST architectures (including memory BIST) and boundary scan.
• Must-have: Experience with ATPG and EDA DFT tools (examples: TestMax, Tetramax, Tessent) and familiarity with PrimeTime.
• Must-have: Gate-level simulation and debugging experience using tools such as VCS or equivalent simulators.
• Must-have: Post-silicon validation and debug experience; familiarity with ATE patterns and IEEE P1687 (embedded instruments).
• Preferred: Verilog design experience for custom DFT logic and IP integration; familiarity with functional verification.
• Preferred: DFT CAD development experience (test architecture, methodology, infrastructure) and Test Static Timing Analysis.
• Preferred: SystemVerilog skills for logic equivalency checking and validating test timing.
• Strong problem-solving and independent debugging ability; effective collaborator across multidisciplinary teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).