ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group as an ASIC Design-for-Test (DFT) Engineer to define, implement, and validate DFT architectures for high-performance networking chips. You will collaborate with front-end RTL, physical design, and validation teams across the full chip implementation and post-silicon phases.

This role focuses on DFT/IP development, chip-level integration, and post-silicon debug to ensure testability, yield, and diagnostic coverage for next-generation silicon.

Experience Level

Senior — posting requires at least 7 years of relevant experience.

Responsibilities

The role is responsible for DFT feature implementation, integration, and validation across implementation and post-silicon phases.

• Design and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop DFT IP and integrate testability features into RTL and full-chip design.
• Collaborate with front-end design, design-verification, and physical-design teams to enable test logic integration and signoff.
• Drive DFT methodology for bare-die and stacked-die device models and reusable test/debug strategies.
• Lead DFT quality processes through implementation flow and post-silicon validation, including involvement in physical-design signoff activities.
• Perform debug and root-cause analysis with minimal mentorship.

Requirements

Must-have technical skills and tools for the role.

• Practical experience with modern DFT, test, and silicon engineering practices.
• Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
• Experience with gate-level simulation and debugging using VCS or similar simulators.
• Post-silicon validation and debug experience, including familiarity with ATE patterns and P1687.
• Verilog experience for custom DFT logic and IP integration; knowledge of functional verification concepts.
• DFT CAD development experience: test architecture, methodology, and infrastructure.
• Test static timing analysis and validating test-timing; SystemVerilog logic equivalency and test-timing validation skills preferred.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required. The posting requires at least 7 years of relevant experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).