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ASIC DFT Engineer

Cisco Systems
July 29, 2026
Full-time
On-site
Austin, Texas, United States
$165,000 - $241,400 USD yearly
DFT Jobs, Level - Senior

Job Title

ASIC DFT Engineer

Role Summary

Join the Silicon One development team as an ASIC DFT Engineer focused on design-for-test (DFT) across RTL, physical implementation, and post-silicon validation. You will define and integrate DFT features, collaborate with front-end and physical-design teams, and drive test and debug strategies for next-generation networking chips.

Experience Level

Senior level β€” requires 7+ years of relevant industry experience.

Responsibilities

Primary responsibilities span DFT IP development, full-chip integration, and validation through implementation and post-silicon phases.

  • Specify, implement, and integrate DFT features to support ATE, in-system test, debug, and diagnostics.
  • Develop reusable DFT IP and coordinate testability features with RTL teams for full-chip integration.
  • Collaborate with physical-design teams to drive DFT requirements during implementation and signoff.
  • Lead post-silicon validation and debug activities, including ATE pattern usage and diagnostics.
  • Contribute to test architecture and methodology for new device models (bare die, stacked die).

Requirements

Clear must-have technical skills and practical experience in DFT, test flows, and post-silicon validation.

Must-have

  • 7+ years of hands-on experience in DFT, test, and silicon engineering.
  • Experience with JTAG protocols, scan and BIST architectures (including memory BIST and boundary scan).
  • Proficiency with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • Gate-level simulation and debugging experience using simulators (e.g., VCS).
  • Post-silicon validation and debug experience, familiarity with ATE patterns and P1687.
  • Ability to craft solutions and debug complex issues with minimal mentorship.

Nice-to-have

  • Verilog/SystemVerilog experience for custom DFT logic and IP integration.
  • DFT CAD development experience: test architecture, methodology, and infrastructure.
  • Test static timing analysis and test-timing validation skills.
  • Experience with SystemVerilog logic equivalency checking and test-timing validation techniques.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies at least 7 years of experience in lieu of additional academic requirements. No certifications were specified.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-07-27