ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Silicon One development organization as an ASIC engineer focused on Design-for-Test (DFT). You will define and implement DFT requirements, develop DFT IP, and drive testability from RTL through implementation and post-silicon validation.

The role requires cross-functional collaboration with front-end RTL, verification, and physical design teams to integrate and validate test logic and support ATE, in-system test, debug, and diagnostics.

Experience Level

Mid-level — this position expects approximately 5+ years of relevant ASIC/DFT/test or silicon engineering experience.

Responsibilities

Key responsibilities include ownership of DFT features and coordination across design and validation phases.

• Implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop reusable DFT IP and integrate testability features into full-chip RTL.
• Collaborate with front-end design, verification, and physical design teams to enable integration and validation of test logic throughout implementation and post-silicon phases.
• Drive DFT and quality processes through implementation flow and post-silicon validation; participate in physical-design signoff activities as needed.
• Contribute to DFT strategies for new silicon models (bare die and stacked die) and help define test and debug approaches.
• Lead debugging and troubleshooting with minimal mentorship; produce actionable fixes and test plans.

Requirements

Concise list of required and preferred technical skills.

• Must-have:
• At least 5 years experience in DFT, test, and silicon engineering.
• Hands-on experience with JTAG protocols, scan architectures, and BIST (including memory BIST and boundary scan).
• Experience with ATPG and EDA DFT toolsets such as TestMax, TetraMAX, Tessent, and PrimeTime.
• Gate-level simulation and debugging experience (e.g., VCS or similar simulators).
• Post-silicon validation and debug experience; familiarity with ATE patterns and P1687.
• Ability to craft solutions and debug complex issues with minimal mentorship and to work across multi-functional teams.
• Nice-to-have:
• Verilog design experience for developing custom DFT logic and IP integration; familiarity with functional verification.
• Test static timing analysis experience.
• Verification skills such as SystemVerilog logic equivalency checking and validating test timing.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies a minimum of 5 years of relevant DFT/test/silicon engineering experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).