ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Silicon One development organization as an ASIC Design-For-Test (DFT) Engineer. You will collaborate with front-end RTL teams and backend physical-design teams to define and implement DFT requirements early in the design cycle and drive testability from implementation through post-silicon validation.

The role is on the Common Hardware Group (CHG) team focused on network silicon platforms; responsibilities include DFT IP development, full-chip integration, and supporting physical-design signoff and post-silicon debug.

Experience Level

Senior. The position requires at least 7 years of relevant experience.

Responsibilities

Primary responsibilities include technical ownership of DFT features and coordination across design and validation phases.

• Implement hardware DFT features to support ATE, in-system test, debug and diagnostics.
• Develop and integrate DFT IP in collaboration with RTL, verification, and physical-design teams.
• Enable integration and validation of test logic throughout implementation and post-silicon flows.
• Contribute to DFT and physical-design aspects for new device models (bare die and stacked die).
• Drive reusable test and debug strategies and participate in test/timing signoff activities.
• Lead DFT quality processes and perform debug with minimal mentorship.

Requirements

Technical must-haves and recommended skills.

• Extensive experience in DFT, test, and silicon engineering (7+ years).
• Experience with JTAG protocols, scan methodologies, BIST architectures (including memory BIST and boundary scan).
• Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
• Gate-level simulation and debugging experience (e.g., VCS or similar simulators).
• Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Ability to design solutions and perform debug with minimal supervision.

• Verilog design experience for custom DFT logic and IP integration; familiarity with functional verification.
• DFT CAD development experience: test architecture, methodology and infrastructure.
• Test static timing analysis and system-verilog logic equivalency/checking for test timing validation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).