ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Lead design-for-test (DFT) activities for ASIC/SoC projects from DFT specification through implementation, verification, and production release. Work with physical design, STA, test engineering and manufacturing teams to meet product test metrics and enable fast silicon bring-up.

Experience Level

Senior — typically 8+ years with a Bachelor's degree or 6+ years with a Master's degree in a relevant engineering field.

Responsibilities

Hands-on execution and technical leadership across DFT architecture, implementation, verification and silicon bring-up.

• Define DFT specifications to meet product and customer testability goals.
• Implement DFT features: scan, MBIST, TAP, LBIST, IO and SerDes integration.
• Perform ATPG, vector generation, verification and debug prior to tape-out.
• Validate and debug test vectors on ATE during silicon bring-up and support RMA.
• Collaborate with STA, physical design, IP DFT engineers, test engineering and customers for timing closure and test integration.
• Assist with failure analysis, diagnostics, yield improvement and production release activities.
• Automate DFT and test-vector generation flows and innovate solutions for advanced nodes (3nm+).

Requirements

Must-have technical skills and experience for this role.

• Strong DFT experience including ATPG, scan insertion/compression, BIST and related flows (tools such as DFT Compiler, Mentor TestKompress, TetraMax, Fastscan).
• Experience with test vector generation, simulation and debugging; Verilog testbench generation and simulation skills.
• Memory BIST insertion and verification experience for embedded memories (SRAM, CAM, eDRAM, ROM).
• Knowledge of boundary-scan (IEEE 1149.1/1149.6) and IEE1687/IJTAG/PDL/ICL.
• Familiarity with Test-STA, timing constraints, and working with STA teams for DFT mode timing closure.
• Proficiency scripting or coding in TCL, Perl, Ruby, Python, C++ or similar for automation.
• Strong debugging, root-cause analysis, data-driven yield improvement and cross-functional communication skills.
• Nice-to-have: ATE experience, SerDes/DDR/PCIe/ENET/CXL IOBIST verification and silicon debug, Tessent SSN experience.

Education Requirements

Bachelor's degree in Electrical, Electronic or Computer Engineering with 8+ years of relevant industry experience, or Master's degree in Electrical, Electronic or Computer Engineering with 6+ years of relevant industry experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.