ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Member of the Common Hardware Group (CHG) within the Silicon One development organization. The role drives Design-for-Test (DFT) requirements and implements DFT IP across RTL, physical design, and post-silicon validation for high-performance networking ASICs.

Work closely with front-end RTL, backend physical design, verification, and validation teams to integrate and validate test logic through implementation and into silicon debug.

Experience Level

Senior — requires at least 7 years of relevant experience in DFT, test, and silicon engineering.

Responsibilities

Primary responsibilities include DFT architecture, integration, validation, and production readiness.

• Define and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP in coordination with multi-functional teams and RTL designers.
• Drive testability requirements early in the design cycle and ensure full-chip DFT integration.
• Collaborate with physical design teams to address DFT-related signoff and implementation issues.
• Support gate-level simulation, test timing validation, and debug during implementation and post-silicon phases.
• Participate in test strategy for new device models (bare die, stacked die) and reusable test/debug approaches.
• Lead post-silicon validation activities and debug using ATE patterns and related tools.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 7+ years experience in DFT, test, and silicon engineering (senior-level contribution expected).
• Hands-on experience with JTAG, scan architectures, BIST (including memory BIST) and boundary scan.
• Experience with ATPG and EDA test tools such as TestMax, Tetramax, Tessent toolsets, and PrimeTime.
• Gate-level simulation and debugging experience using simulators like VCS.
• Post-silicon validation and debug experience, familiarity with ATE patterns and P1687.
• Ability to design solutions and debug independently with minimal mentorship.

Nice-to-have:

• Verilog design experience for custom DFT logic and IP integration.
• DFT CAD development experience: test architecture, methodology, and infrastructure.
• Test static timing analysis (Test STA) and test-timing validation skills.
• Familiarity with SystemVerilog equivalency checking and functional verification techniques.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).