ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Work within Cisco's Silicon One development organization to design and implement design-for-test (DFT) features and IP for high-performance networking ASICs. Collaborate with front-end RTL teams, backend physical design teams, and validation groups across the full implementation and post-silicon lifecycle.

This role focuses on DFT architecture, IP development, chip-level integration, and post-silicon debug for modern device models (bare die, stacked die) with emphasis on testability, diagnostics, and production test flow.

Experience Level

Senior — requires 7+ years of relevant ASIC/DFT experience.

Responsibilities

Primary responsibilities center on DFT architecture, IP development, integration, validation and post-silicon debug.

• Specify and implement DFT features to support ATE, in-system test, debug and diagnostics.
• Develop and integrate DFT IP with RTL and full-chip designs; ensure testability features are coordinated with front-end teams.
• Work with physical design teams to address DFT-related implementation and signoff issues.
• Drive ATPG, pattern generation, and validation across implementation and post-silicon phases.
• Participate in test strategy for new silicon models (bare die, stacked die) and develop reusable test/debug methodologies.
• Lead debugging and problem resolution with limited supervision during implementation and post-silicon validation.

Requirements

Must-have technical skills and tools experience; preferred items noted separately.

• Must-have: Strong background in DFT, test, and silicon engineering with hands-on experience in scan, JTAG, BIST (including memory BIST) and boundary-scan architectures.
• Must-have: Experience with ATPG and industry EDA DFT toolsets (examples: TestMax/Tetramax, Tessent, PrimeTime) and gate-level simulation/debug with tools such as VCS.
• Must-have: Post-silicon validation and debug experience, including working with ATE patterns and P1687 (or equivalent)
• Nice-to-have: Verilog/RTL development for custom DFT logic and IP integration; familiarity with functional verification practices.
• Nice-to-have: DFT CAD development experience covering test architecture, methodology and infrastructure; test static timing analysis.
• Nice-to-have: SystemVerilog skills for logic equivalency checking and validating test timing.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required (as stated in the posting). The role also specifies at least 7 years of relevant ASIC/DFT experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).