ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Member of the Silicon One development organization focused on Design-for-Test (DFT). Work with front-end RTL and back-end physical design teams to define and integrate testability features across implementation and post-silicon validation.

Team develops hardware platforms for networking silicon; this role contributes DFT IP, integration, and debug strategies for next-generation ASICs.

Experience Level

Mid-level — this role expects experienced engineers (approximately 5+ years of relevant DFT, silicon test, or related experience).

Responsibilities

The engineer will lead DFT activities across the design and validation flow.

• Specify and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP in collaboration with multi-functional RTL and physical-design teams.
• Drive DFT and testability requirements early in the design cycle and through full-chip integration.
• Work with design, verification, and PD teams to enable integration and validation of test logic during implementation and post-silicon flows.
• Support post-silicon validation, ATE pattern usage, and debug activities.
• Contribute to test and debug strategies for new device models (bare die, stacked die) and promote re-usable approaches.
• Participate in physical-design signoff activities related to testability and test timing.

Requirements

Core technical skills and domain experience required; preferred skills listed separately.

• Must-have: Practical experience with DFT techniques including JTAG, scan architectures, BIST (including memory BIST), and boundary scan.
• Must-have: Experience with ATPG and commercial EDA DFT toolsets (examples: TestMax, Tetramax, Tessent) and familiarity with PrimeTime for timing analysis.
• Must-have: Gate-level simulation and debugging experience using simulators such as VCS.
• Must-have: Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Nice-to-have: Verilog/SystemVerilog design and functional verification experience, including logic equivalency checking and test-timing validation.
• Nice-to-have: Experience with Test Static Timing Analysis and developing custom DFT IP for integration into RTL.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required. The posting specifies at least 5 years of related experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).