ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group (CHG) within the Silicon One development organization as an ASIC Engineer focused on Design-for-Test (DFT). The role drives DFT requirements early in the design cycle and supports testability through implementation and post-silicon validation.

The engineer will collaborate with front-end RTL, verification, and backend physical design teams to develop and integrate DFT IP and enable ATE, in-system test, debug, and diagnostics for next-generation networking chips.

Experience Level

Mid-level — minimum 5 years of relevant industry experience.

Responsibilities

Primary responsibilities include defining, implementing, and validating DFT and testability features across RTL, implementation, and post-silicon phases.

• Implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP into full-chip RTL in collaboration with multi-functional teams.
• Work with front-end design, verification, and physical design teams to enable and validate test logic during implementation and post-silicon validation.
• Contribute to DFT strategies for new device models (bare die, stacked die) and reusable test/debug approaches.
• Drive DFT and quality processes through implementation flow and post-silicon validation, with exposure to physical design signoff activities.
• Troubleshoot and debug DFT/test issues with minimal mentorship.

Requirements

Must-have technical skills and experience required to perform the role; preferred items listed separately.

• Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Hands-on experience with ATPG and EDA DFT toolsets (examples: TestMax, Tetramax, Tessent) and familiarity with PrimeTime.
• Experience with gate-level simulation and debugging using simulators such as VCS.
• Post-silicon validation and debug experience, including working with ATE patterns and IEEE P1687 (IJTAG) concepts.
• Ability to design and integrate custom DFT logic/IP and coordinate testability features in RTL.
• Strong debugging skills and ability to craft solutions with minimal supervision.

Preferred:

• Verilog design experience for custom DFT logic and IP integration.
• Familiarity with functional verification and SystemVerilog-based logic equivalency checking.
• Experience with test static timing analysis and validating test timing.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or Computer Engineering required. The position specifies a minimum of 5 years of relevant industry experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).