ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group to design and integrate design-for-test (DFT) features for high-performance networking ASICs. The role partners with front-end RTL, physical design, and validation teams to define, implement, and validate testability, debug, and ATE support across implementation and post-silicon phases.

Experience Level

Senior — requires substantial hands-on experience; posting specifies at least 7 years of relevant experience.

Responsibilities

Accountable for planning, implementing, and validating DFT capabilities and processes across the full chip lifecycle.

• Design and implement DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop reusable DFT IP and integrate testability features with RTL and full-chip designs.
• Collaborate with design, design-verification, and physical-design teams to validate test logic during implementation and post-silicon validation.
• Contribute to DFT and physical-design strategies for new silicon types (bare die, stacked die) and drive reusable test/debug methodologies.
• Lead DFT and quality processes through implementation flow and post-silicon validation; support physical-design signoff activities.
• Diagnose and debug complex test issues with minimal mentorship.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• 7+ years of experience in DFT, test, and silicon engineering.
• Hands-on experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
• Gate-level simulation and debugging experience using VCS or comparable simulators.
• Post-silicon validation and debug experience; familiarity with ATE patterns and P1687.
• Ability to craft solutions and debug complex issues with minimal oversight.

Preferred / nice-to-have:

• Verilog/SystemVerilog design experience for custom DFT logic and IP integration; functional verification experience.
• DFT CAD development experience (architecture, methodology, infrastructure).
• Test static timing analysis and test-timing validation skills.
• SystemVerilog logic equivalency checking and test-timing validation experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required. The posting specifies a minimum of 7 years of relevant experience. No alternative-equivalent-experience language was provided.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).