ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group (CHG) within the Silicon One development organization as an ASIC Design-for-Test (DFT) Engineer. The role partners with front-end RTL, backend physical design, verification, and manufacturing teams to define, implement, and validate DFT features across implementation and post-silicon validation phases.

Experience Level

Senior — requires substantial prior experience. (See Education Requirements for formal degree and years guidance.)

Responsibilities

Deliver and integrate DFT solutions across the full chip lifecycle, from RTL collaboration through post-silicon validation and physical design signoff.

• Define and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop DFT IP and integrate testability features into RTL and full-chip designs.
• Collaborate with RTL, design-verification, physical design, and CAD teams to enable test logic integration and validation.
• Lead DFT strategy for new device models including bare die and stacked die; promote re-usable test and debug approaches.
• Drive ATPG flows, fault coverage analysis, and test pattern generation through tool flows and signoff.
• Support post-silicon validation and ATE pattern development and debug.
• Debug complex test and silicon issues with minimal mentorship and provide implementation guidance to cross-functional teams.

Requirements

Must-have technical skills and experience; education details appear in the Education Requirements section below.

• Hands-on DFT experience with JTAG, scan architectures, boundary scan, and memory BIST.
• Experience with ATPG and commercial EDA tools (examples: TestMax, Tetramax, Tessent tool sets, PrimeTime).
• Gate-level simulation and debug experience with VCS or equivalent simulators.
• Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Ability to drive DFT integration and validation across implementation and post-silicon phases.

Nice-to-have / preferred:

• Verilog design experience for custom DFT logic and IP integration; familiarity with functional verification.
• DFT CAD development: test architecture, methodology, and infrastructure.
• Experience with Test Static Timing Analysis and SystemVerilog logic equivalency checking.

Education Requirements

Required: Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering. Minimum ~7 years of relevant DFT/test/silicon engineering experience. (The posting specifies degree requirement and the 7+ years experience minimum.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).