ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group (CHG) within the Silicon One development organization to design and integrate Design-for-Test (DFT) features for next-generation networking ASICs. The role partners with front-end RTL, backend physical design, and verification teams to define DFT requirements, drive implementation, and support post-silicon validation.

Experience Level

Senior — requires at least 7 years of relevant experience.

Responsibilities

Primary responsibilities center on DFT architecture, IP development, chip-level integration, and validation across implementation and post-silicon phases.

• Specify and implement DFT features for ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP in collaboration with RTL, verification, and PD teams.
• Drive full-chip DFT integration and ensure testability is coordinated across RTL and physical design flows.
• Support gate-level simulation, test-timing validation, and post-silicon debug activities.
• Contribute to test strategies for bare die and stacked-die devices and reusable debug methodologies.
• Troubleshoot and produce solutions with minimal mentorship during implementation and post-silicon validation.

Requirements

Must-have skills and experience for the role; preferred items are listed separately.

• Extensive experience in DFT, test, and silicon engineering (minimum 7 years experience expected; degree details in Education Requirements).
• Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Familiarity with ATPG and EDA tools such as TestMax, TetraMAX, Tessent tool sets, and PrimeTime.
• Experience with gate-level simulation and debugging using VCS or similar simulators.
• Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Ability to integrate custom DFT logic and coordinate with functional verification teams.

Nice-to-have:

• Verilog/SystemVerilog design and verification experience (logic equivalency checking, test-timing validation).
• DFT CAD development, test architecture, methodology and infrastructure experience.
• Experience with Test Static Timing Analysis and advanced post-silicon validation techniques.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies a degree in these fields along with the minimum experience noted above.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).