ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Silicon One development organization as an ASIC DFT Engineer focused on design-for-test (DFT) across RTL, physical design, implementation, and post-silicon validation. The role works with front-end RTL teams, backend physical design teams, and cross-functional stakeholders to define, implement, and validate DFT IP and test strategies for advanced networking ASICs.

Experience Level

Senior — position expects at least 7 years of relevant industry experience.

Responsibilities

Contribute to DFT architecture, implementation, integration, and validation across the full chip lifecycle, including post-silicon debug and physical-design signoff activities.

• Define and implement DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP in collaboration with RTL, verification, and physical-design teams.
• Drive full-chip testability features and coordinate test logic integration across implementation flows.
• Support post-silicon validation: ATE patterns, debug, and diagnostics; collaborate on bring-up and lab validation.
• Participate in test architecture and methodology for new silicon device models (bare die, stacked die) and reusable test/debug strategies.
• Work with EDA and CAD teams to enable ATPG, test automation, and signoff-quality test flows.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Minimum 7+ years of experience in DFT, test, or silicon engineering.
• Hands-on experience with JTAG, scan-based test, BIST architectures (including memory BIST), and boundary scan.
• Experience with ATPG and DFT/EDA toolsets such as TestMax, Tetramax, Tessent, and PrimeTime.
• Gate-level simulation and debug experience using simulators (e.g., VCS) and related debug flows.
• Post-silicon validation experience including ATE patterns and IEEE P1687 (IJTAG) use.
• Verilog-based design experience for custom DFT logic and IP integration; familiarity with functional verification concepts.
• DFT CAD development, test architecture, methodology, and infrastructure experience.
• Nice-to-have: Test static timing analysis and SystemVerilog logic equivalency checking, and verification of test timing.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).