ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Work within the Silicon One development organization to define, implement, and validate Design-for-Test (DFT) features across RTL, physical design, implementation, and post-silicon validation phases. Collaborate with front-end RTL, verification, and backend physical design teams to deliver testable, debuggable networking ASICs and DFT IP.

Experience Level

Senior — requires at least 7 years of relevant DFT, test, or silicon engineering experience.

Responsibilities

Primary responsibilities include driving DFT architecture, integration, and validation throughout the chip development cycle.

• Implement DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate DFT IP in collaboration with multi-functional teams and coordinate testability features in RTL.
• Work with design, verification, and physical design teams to enable integration and validation of test logic during implementation and post-silicon validation.
• Contribute to DFT and physical design strategies for new silicon device models (bare die and stacked die) and drive reusable test and debug approaches.
• Lead DFT and quality processes through implementation flow and post-silicon validation phases.
• Independently craft solutions and debug complex issues with minimal mentorship.

Requirements

Must-have technical skills and preferred qualifications are listed below.

• Must-have: 7+ years of experience in DFT, test, or silicon engineering.
• Hands-on experience with JTAG protocols, scan architectures, and BIST (including memory BIST and boundary scan).
• Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
• Gate-level simulation and debugging experience using VCS or similar simulators.
• Post-silicon validation and debug experience; familiarity with ATE patterns and IEEE P1687 (or similar).
• Ability to design solutions and debug issues independently.

Nice-to-have:

• Verilog design experience for custom DFT logic and IP integration; familiarity with functional verification.
• DFT CAD development experience: test architecture, methodology, and infrastructure.
• Test static timing analysis and test-timing validation skills.
• Verification skills including SystemVerilog logic equivalency checking.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).