ASIC Design Verification Technical Leader

Job Title

ASIC Design Verification Technical Leader

Role Summary

Lead verification for silicon photonics driver integrated circuits within Cisco's Client Optics Group, defining verification methodology and standards across projects and sites. Drive verification from block to chip level, influence architecture for testability, and mentor verification engineers to deliver large-scale SoCs and subsystems.

Experience Level

Senior — senior-level technical leader. Typical expectation: substantial prior experience leading ASIC design verification efforts and verification teams.

Responsibilities

The role owns verification strategy and execution across multiple projects and sites.

• Define and enforce verification methodology, standards, and best practices across projects.
• Lead verification efforts at block and chip level for high-speed IPs (ODSP, D2D PHY, SerDes XSR/PAM4, integrated drivers/TIA, control functions).
• Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.
• Mentor and coach verification engineers; drive continuous technical improvement and execution.
• Debug complex silicon and system-level issues during bring-up and support post-silicon validation.
• Coordinate verification activities across multiple sites and with architecture/design teams.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven experience with SystemVerilog and UVM-based verification methodologies.
• Track record owning and delivering verification for large-scale SoCs or subsystems.
• Experience leading verification teams or projects and driving cross-site coordination.
• Scripting and automation experience (Python, Perl, TCL, or shell scripting).
• Strong troubleshooting and debugging skills for complex hardware and integration issues.

Nice-to-have / Preferred:

• Deep UVM expertise for scalable, reusable, coverage-driven environments.
• Experience verifying SerDes IP, D2D PHY IP, ODSP, integrated transceiver features, and CPU subsystems or relevant protocols (Ethernet, UCIE, UAL, SPI/I2C).
• Experience with formal verification and hardware description languages.
• Familiarity with emulation and prototyping platforms (for example, Veloce, HAPS).
• Experience influencing design for testability and collaborating on verification strategy.

Education Requirements

The posting specifies degree-based qualifications: a Bachelor's degree in Electrical or Computer Engineering with 8+ years of ASIC design verification experience; a Master’s degree in Electrical or Computer Engineering with 6+ years of ASIC design verification experience; or a PhD in Electrical or Computer Engineering with 3+ years of ASIC design verification experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).