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ASIC Design Verification Manager / Sr. Manager

Synopsys
September 17, 2026
Full-time
On-site
Hsinchu, Taiwan
Verification Jobs, Level - Senior

Job Title

ASIC Design Verification Manager / Sr. Manager

Role Summary

Lead a verification team responsible for design and verification of synthesizable DesignWare IP cores, with a focus on high-performance memory controller IPs (HBM/DDR/LPDDR). Work with RTL designers, architects, and verification engineers across global sites to deliver product releases.

This is a hands-on leadership role combining technical contribution in RTL and UVM testbench development with people and project management to meet verification milestones.

Experience Level

Senior - role expects extensive experience; the posting specifies 15+ years of relevant verification/IP experience.

Responsibilities

Primary responsibilities include technical leadership, delivery oversight, and driving verification quality.

  • Specify, architect, and implement IP design and verification environments for synthesizable DesignWare cores.
  • Lead and mentor a team of engineers; assign tasks and drive closure of day-to-day design and verification activities.
  • Collaborate with RTL designers, architects, and verification engineers in a global team structure.
  • Develop RTL code, unit- and system-level test plans, and UVM-based testbenches.
  • Manage regression debug triage and verification activities to meet product release milestones.
  • Contribute to development and verification of next-generation DesignWare HBM IPs and process improvements.

Requirements

Required technical skills and leadership traits for immediate contribution.

  • 15+ years of relevant experience in verification of IP cores and/or SoC, including team leadership.
  • Hands-on experience in RTL design and/or verification at the IP or SoC level.
  • Strong knowledge of Verilog and SystemVerilog; experience developing UVM testbenches.
  • Experience with memory protocols such as HBM, DDR, and LPDDR.
  • Proficiency in scripting and automation using Perl and Python; familiarity with shell scripting.
  • Proven communication, problem-solving skills, and ability to work in multi-site teams.
  • Experience improving coverage metrics, defining additional test cases, and using IP design/verification tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics/Computer Engineering, VLSI or a closely related field (BS/MS in EE/EC/VLSI as specified).


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-09-15