ASIC Design Verification Engineer - Vancouver or Markham
QualcommJob Title
ASIC Design Verification Engineer - Vancouver or Markham
Role Summary
Join the ASIC verification team responsible for the full verification lifecycle from system concept through tape-out and post-silicon support. The role focuses on pre-silicon test planning for digital power IP, creating and maintaining advanced verification environments, and developing automation to increase verification efficiency.
Experience Level
Mid-level. Minimum experience expectations: typically 2+ years of ASIC design/verification experience (Master's may reduce required experience to 1+ year); senior candidates with ~6+ years are preferred for more advanced responsibilities.
Responsibilities
Primary responsibilities include planning and executing verification tasks and building robust test environments.
- Develop block-level and system-level testbenches using SystemVerilog and UVM.
- Create functional coverage, assertion models, and formal property checks.
- Plan and execute pre-silicon verification for digital power IP and participate in post-silicon debug.
- Implement power-aware verification flows (UPF) and related methodology.
- Develop automation and scripts to improve verification throughput and repeatability.
- Collaborate with architects, RTL designers, and validation teams to close verification gaps.
Requirements
Must-have technical skills and experience are listed first; preferred skills are noted separately.
- Must-have: 2+ years of ASIC design, verification, validation, or integration experience.
- Must-have: Experience developing testbenches and verification environments using SystemVerilog and UVM.
- Must-have: Experience with functional coverage, assertion-based verification, and formal verification techniques.
- Must-have: Scripting or automation experience (e.g., Python or Perl) to support verification flows.
- Nice-to-have: Strong RTL design knowledge (SystemVerilog/Verilog/VHDL) and C/C++ programming skills.
- Nice-to-have: Experience with AMBA bus protocols (AXI/AHB/APB).
- Nice-to-have: Prior exposure to power-aware verification (UPF) and post-silicon bring-up.
Education Requirements
Minimum: Bachelor's degree in Engineering, Science, or a related field plus 2+ years of relevant ASIC design/verification experience. Alternatives listed: Master's degree in Science or Engineering with 1+ year experience, or a PhD in a related field. Preferred fields include Electrical Engineering, Computer Engineering, Computer Science, or closely related technical disciplines.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
