ASIC Design Verification Engineer II
Cisco SystemsJob Title
ASIC Design Verification Engineer II
Role Summary
Work on the Silicon One ASIC verification team to validate data-center switching and routing silicon through simulation, emulation, and ASIC bring-up. The role is focused on building and maintaining verification environments, developing directed and constrained-random tests, and driving module verification closure in collaboration with designers and cross-functional hardware teams.
Experience Level
Mid-level. Typical candidates have roughly 2+ years of verification or ASIC-related experience and practical experience with verification methodologies and scripting.
Responsibilities
The engineer will develop and maintain verification infrastructure and tests to achieve functional completeness and quality for ASIC blocks and integrations.
- Maintain and enhance existing design verification (DV) environments.
- Construct testbenches: agents, sequencers, monitors, scoreboards.
- Write test plans and develop test cases for block and cluster verification.
- Run regressions, debug failures, and drive issues to closure.
- Implement and review code and functional coverage to ensure verification completeness.
- Verify designs in simulation, emulation, and during ASIC bring-up; collaborate with designers, hardware, and cross-functional teams.
Requirements
Key technical skills and practical experience required or preferred for success in this role.
Must-have:
- Practical experience with SystemVerilog and UVM methodology for ASIC verification.
- Experience developing and maintaining constrained-random verification environments and functional coverage.
- Scripting experience (Perl and/or Python) for test automation and regression management.
- Ability to debug regression failures and drive verification to closure.
Nice-to-have:
- Experience verifying complex blocks, clusters, and top-level SoC integrations.
- Experience with emulation platforms such as Veloce or HAPS.
- Experience building testbenches from scratch, including constraints, structures, and class-based designs in SystemVerilog.
- Effective verbal and written communication skills for cross-team collaboration.
Education Requirements
One of the following: a Master’s degree (qualifying education completed within the past 3 years or expected within the next 12 months) or a Bachelor’s degree plus ~2 years of relevant work experience. Qualifying fields include ASIC engineering, verification, or related technical disciplines. Equivalent practical experience in verification or ASIC engineering may also be acceptable.
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
