ASIC Design Verification Engineer

Job Title

ASIC Design Verification Engineer

Role Summary

Own the verification strategy and coverage closure for AMD's mixed-signal power management IP. Drive system-level verification of the full SoC, contribute to block-level verification and SystemVerilog RTL design, and support post-silicon bring-up and cross-functional debugging.

Work with Analog, Firmware, Systems Engineering, and Architecture teams to ensure verified behavior matches silicon intent. This role is not eligible for visa sponsorship.

Experience Level

Mid-level. The posting does not state specific years of experience.

Responsibilities

Key responsibilities include ownership of verification strategy, system- and block-level verification, and cross-team collaboration.

• Own verification strategy, test plan, and coverage closure for a mixed-signal power management IC.
• Define functional and code coverage goals; track progress and report verification status and readiness.
• Own verification signoff criteria and drive the team to coverage closure ahead of tape-out.
• Maintain and improve regression infrastructure, triage flow, and results reporting.
• Develop and execute system-level verification of the full SoC (boot/reset sequencing, power-state transitions, fault/protection scenarios, host interface traffic).
• Verify firmware-driven behavior via co-simulation of embedded firmware with RTL.
• Build and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level.
• Develop block-level testbenches and coverage for digital blocks as required and verify digital/analog interfaces using real-number models (RNM) or Verilog-AMS.
• Partner with Analog and RTL designers on design reviews, verification planning, and failure debug to root cause; support post-silicon correlation.
• Mentor junior engineers and lead verification reviews and methodology adoption.

Requirements

Required skills and tools for successful performance in this role, plus preferred additions.

• Must-have: Strong SystemVerilog and UVM testbench development skills with ownership of verification for a block or subsystem through tape-out.
• Must-have: Ability to read and understand RTL and design specifications and to derive test intent independently.
• Must-have: Proven experience with coverage-driven verification: defining verification plans, setting functional and code coverage goals, and driving closure.
• Must-have: Proficiency with simulation, coverage, and debug tools and experience with regression automation.
• Nice-to-have: System-level or SoC-level verification ownership on mixed-signal devices; firmware/RTL co-simulation or hardware/software co-verification experience.
• Nice-to-have: Real-number modeling (RNM) of analog blocks in SystemVerilog or Verilog-AMS; formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience.
• Nice-to-have: Post-silicon bring-up and debug experience and experience mentoring engineers and leading verification reviews.

Education Requirements

Bachelor's or master's degree in Electrical or Computer Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.