ASIC Design Engineer — Video Silicon IP (Multimedia Lab)

Job Title

ASIC Design Engineer — Video Silicon IP (Multimedia Lab)

Role Summary

Join ByteDance's Video Silicon IP team in San Jose to design hardware accelerators and RTL for multi-standard video codec and processing IP. Collaborate with architecture, algorithm, verification and physical-design teams to deliver efficient, low-power video-processing blocks.

Experience Level

Entry-level — expects approximately 2 years of ASIC front-end design experience as the primary RTL owner.

Responsibilities

Primary responsibilities include architecting and delivering RTL for video codec pipeline stages and working with verification and physical design to achieve functional and timing closure.

• Design micro-architectures and hardware accelerators for video encoding and processing (prediction, transform, quantization, entropy coding, etc.).
• Translate codec standards and algorithmic improvements into hardware architectures for multi-standard codec cores.
• Implement RTL (SystemVerilog or HLS) and drive functional correctness with verification using UVM testbenches.
• Debug RTL, close coverage goals, and work with verification engineers to resolve issues.
• Collaborate with synthesis and physical-design teams on timing closure, floorplanning, and CDC/RDC checks.
• Optimize designs for area, power, and performance targets.
• Automate and validate EDA flows and pre-silicon validation tasks (including FPGA prototyping when applicable).

Requirements

Must-have technical skills and experience.

• 2+ years ASIC front-end design experience as the primary RTL owner.
• Proficiency in SystemVerilog RTL design or High-Level Synthesis (HLS).
• Familiarity with UVM, DPI and C++ for verification environments.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces, and basic SV assertions.
• Scripting proficiency in Python for EDA flow automation.
• Practical knowledge of synthesis, timing analysis, CDC/RDC issues and collaboration with physical-design teams.

Nice-to-have:

• Experience with video codec standards (H.265/HEVC, H.266/VVC, AV1, VP9, H.264/AVC).
• Experience with ISP or ML-based image/video compression.
• FPGA prototyping experience for pre-silicon codec validation.
• Practical use of LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL workflows.

Education Requirements

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (the posting specifies M.S./Ph.D.).

About the Company

Company: ByteDance

Headquarters: Beijing, China

ByteDance is a Beijing-based multinational internet technology company known for consumer apps like TikTok and Toutiao. The company develops AI-driven content platforms, advertising products, and research in machine learning, video technologies, and cloud services.