ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems

Job Title

ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems

Role Summary

Join an SoC design team responsible for interconnects, cache and memory subsystems, and high-speed DDR memory controllers for mobile and compute platforms. The role partners with architecture, verification, physical design, and software teams to deliver high-performance, power-efficient silicon.

Experience Level

Mid-level; approximately 0–4+ years of industry or relevant academic experience.

Responsibilities

Design and deliver RTL and related artifacts for SoC interconnects, cache and memory subsystems, and DDR controllers; participate across the full product development cycle.

• Define microarchitecture and write design specifications for complex SoC subsystems.
• Design, implement, and validate Verilog/SystemVerilog RTL for interconnects, cache controllers, memory subsystems, and DDR controller components.
• Collaborate with system architects to evaluate feature feasibility and performance trade-offs.
• Optimize designs for performance, power, area, timing, and scalability.
• Work with verification teams to develop test plans, review coverage, debug issues, and meet quality goals.
• Support synthesis, timing closure, power analysis, gate-level simulation, and physical design activities.
• Participate in system-level integration, silicon bring-up, and post-silicon debugging.
• Contribute to C/C++ modeling, scripting (Python), design methodologies, and process improvements.

Requirements

Core qualifications and skills required to perform the role.

• 0–4+ years of relevant industry or academic experience in ASIC/SoC design.
• Hands-on experience or coursework in Verilog and/or SystemVerilog RTL design.
• Knowledge of computer architecture and digital logic design.
• Experience programming in C, C++, and/or Python for modeling or tooling.
• Familiarity with ASIC design methodologies (synthesis, timing closure, power analysis).
• Strong analytical, problem-solving, communication, and collaboration skills.

Nice-to-have:

• SoC interconnects, on-chip communication fabrics, cache and memory subsystem design.
• DDR/LPDDR memory controller architecture and design, HBM experience.
• ARM or x86 processor architectures and bus protocols; RTL for CPUs or cache controllers.
• Low-power design methodologies, functional and coverage-driven verification techniques.
• Experience with Synopsys synthesis tools, physical design flows, timing closure, and silicon bring-up.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field are listed as acceptable. The posting also accepts equivalent relevant academic experience in lieu of industry experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.