ASIC Design Engineer, DMTS/SMTS/MTS

Job Title

ASIC Design Engineer, DMTS/SMTS/MTS

Role Summary

Lead development and enablement of CAD tools, automation, and physical design flows for advanced semiconductor products (NAND, DRAM, HBM, SoC, mixed-signal). Collaborate with architecture, RTL, verification, process, and product teams to deliver design implementations and silicon bring-up.

The role combines tool and flow development, physical design signoff, custom layout and DFT, and technical leadership across global engineering teams.

Experience Level

Mid-level. No explicit years-of-experience specified in the posting.

Responsibilities

Primary responsibilities include CAD/tool development, design implementation, signoff, and cross-team technical leadership.

• Develop, deploy, and support scalable CAD tools, automation frameworks, and design methodologies for memory, SoC, and mixed-signal products.
• Build and maintain infrastructure for capture, layout, simulation, extraction, implementation, verification, and signoff workflows.
• Create and maintain scripts and software (Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp) to automate engineering workflows and analytics.
• Evaluate and integrate EDA technologies and AI-assisted solutions to improve productivity, scalability, and silicon quality.
• Lead physical design activities: floorplanning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification.
• Own multi-mode, multi-corner timing signoff, constraints, timing exceptions, signal integrity, ECOs, and closure across implementation steps.
• Develop and implement DFT strategies (scan insertion, ATPG, MBIST, LBIST, compression) and support silicon bring-up and manufacturing test coverage goals.
• Analyze and resolve congestion, IR drop, electromigration, clocking, signal integrity, and implementation issues across the design cycle.
• Lead custom layout, parasitic extraction, post-layout correlation, and layout verification (DRC, LVS, reliability).
• Provide technical leadership, mentorship, documentation, training, and cross-functional support to ensure tape-out and production ramp success.

Requirements

Key technical skills and experience required or preferred.

Must-have:

• Strong knowledge of VLSI and CMOS fundamentals, semiconductor build methodologies, and tradeoffs involving power, performance, area, reliability, and manufacturability.
• Hands-on experience with industry-standard EDA flows and tools for implementation, timing, test, simulation, extraction, layout, verification, and signoff (examples: Cadence Innovus/Virtuoso, Synopsys ICC2/PrimeTime, Cadence Tempus/Modus, Siemens Tessent, or equivalents).
• Proficiency in Unix/Linux and one or more scripting/programming languages such as Python, Tcl, SKILL, Shell, Perl, C/C++, Java, or Lisp.
• Proven ability to develop maintainable automation, debug complex design and flow issues, analyze engineering data, and drive designs to closure.

Nice-to-have:

• Experience applying AI-assisted engineering techniques to tooling and workflows.
• Prior work on memory products (NAND, DRAM, HBM), large SoCs, or mixed-signal designs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field - or equivalent proven experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.