ASIC Design Engineer - DFT & Physical Design (Experienced / Lead / Senior)

Job Title

ASIC Design Engineer - DFT & Physical Design (Experienced / Lead / Senior)

Role Summary

Work on design-for-test (DFT) architectures and physical design (synthesis and static timing analysis) for advanced digital subsystems used in mission-critical aerospace applications. The role focuses on DFT infrastructure, ATPG and memory test flows, timing closure, and silicon validation.

Based in Mountain View, CA within Boeing Defense, Space & Security. Responsibilities range from individual contributor tasks to technical leadership and mentoring at senior/lead levels.

Experience Level

Senior-level (Experienced / Lead). The posting requests approximately 5+ years of ASIC/FPGA experience in DFT or physical design, with leadership expectations for senior/lead roles.

Responsibilities

Primary responsibilities include DFT architecture and test infrastructure, synthesis and timing activities, silicon validation, and cross-team coordination.

• Design and implement DFT architectures and test access mechanisms (TAP/JTAG, IJTAG, Boundary Scan).
• Develop and validate TAP/JTAG and IJTAG infrastructures; support ATPG pattern generation and MBIST flows.
• Drive pattern generation, memory test validation, silicon debug, and post-silicon validation.
• Perform synthesis, equivalence checking, static timing analysis, and timing convergence at block and chip levels.
• Support clean netlist handoffs and timing closure by collaborating with RTL, verification, and backend teams.
• Troubleshoot complex timing and CDC issues and implement robust solutions.
• Coordinate with external partners on custom DFT interfaces and backend flows.
• Contribute to methodology development, automation, and best practices for next-generation products.
• Mentor engineers and lead technical efforts for senior/lead roles.

Requirements

Must-have technical skills and security eligibility; listed nice-to-have items are supplemental.

• Must-have: US Citizenship and ability to obtain a US security clearance.
• Must-have: Approximately 5+ years of ASIC/FPGA experience in DFT or physical design (synthesis, STA).
• Must-have: Hands-on experience with DFT tools and methodologies (e.g., TAP/JTAG, MBIST) and practical experience in synthesis and static timing analysis.
• Must-have: Proficiency in scripting for automation and analysis (Tcl, Python, Perl).
• Nice-to-have: Experience with ATPG pattern generation, memory test validation, silicon debug, and post-silicon validation.
• Nice-to-have: Experience coordinating with external partners and custom backend flows.
• Nice-to-have: Prior mentoring or technical leadership experience.

Education Requirements

Bachelor's degree in Engineering, Computer Science, or a related technical field (required as stated). No alternative degree equivalence or preferred graduate degrees were specified in the posting.

About the Company

Company: Boeing

Headquarters: Arlington, Virginia, United States

Large U.S. aerospace and defense company that designs, manufactures, and services commercial airplanes, military aircraft, satellites, and related systems and services worldwide.