ASIC Design Engineer

Job Title

ASIC Design Engineer

Role Summary

Positron AI seeks a senior ASIC design engineer to define microarchitecture and deliver production-quality SystemVerilog RTL for high-performance AI inference SoCs. The role partners with physical design, verification, architecture, and vendors to meet performance, power, and area (PPA) targets and support silicon bring-up and post-silicon debug.

Experience Level

Senior — requires 8+ years of ASIC/SoC RTL design experience.

Responsibilities

Drive design and integration of complex IP blocks and subsystems, ensuring they meet PPA and integration requirements.

• Define and document microarchitecture for complex IP blocks and subsystems.
• Deliver parameterized, production-quality SystemVerilog RTL with well-defined interfaces and embedded assertions.
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with physical design on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
• Architect and integrate high-performance interconnects, DMA engines, coherency logic, and high-speed memory interfaces.
• Engage with IP vendors and internal stakeholders for seamless integration.
• Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
• Contribute automation flows and partner with Verification and Architecture teams on test plans, reference models, and RTL correlation.
• Support bring-up, post-silicon debug, customer engagements, mentor junior engineers, and lead design reviews.

Requirements

Must-have technical skills and delivery experience; nice-to-have items listed separately.

• Proven track record leading designs from specification to RTL signoff with strong PPA outcomes.
• Deep expertise in SystemVerilog RTL, including clocking, resets, and protocol correctness.
• Extensive experience with front-end flows and major EDA tool suites.
• Hands-on experience with HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, and high-throughput datapaths.
• Experience driving PPA optimizations and collaborating with physical design for timing closure.
• Strong cross-functional communication skills and experience working with IP vendors.
• Nice-to-have: AI/ML accelerator design, low-power design techniques, formal verification/SVA, cocotb/UVM experience, RISC-V subsystems and coherence protocols.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies 8+ years of ASIC/SoC RTL design experience.

About the Company

Company: Positron AI

Positron AI designs custom hardware systems and SoC solutions to accelerate AI inference, focusing on high-performance, energy-efficient alternatives to traditional GPU-based inference platforms.