ASIC Design Engineer, Clocks
This role is a design engineering position on the NVIDIA GPU clocks team responsible for architecting, designing and validating clock RTL for GPU products. The team interfaces with frontend architects, backend physical-design teams, SOC verification, timing and DFT groups.
The engineer will deliver high-frequency, low-power clocking logic, run and improve internal flows for RTL and netlist quality, and support silicon bring-up and debug with software and silicon-solution teams.
Senior-level. The posting indicates approximately 2+ years of meaningful work experience; the role title is Senior.
Core responsibilities include design, validation, and cross-team delivery of GPU clocking features.
Key technical and interpersonal requirements. Education details are summarized separately below.
BS required or MS preferred in Electrical Engineering (EE) or equivalent experience; the posting allows equivalent practical experience in lieu of degree. The source also references 2+ years of meaningful work experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
