ASIC Design Engineer - Cache Controller
Design and develop cache subsystem hardware and micro-architecture for high-performance system-on-chip (SoC) memory hierarchies. Work spans architecture trade-off analysis, RTL implementation, and collaboration with physical design for timing and area closure.
Entry-level. The posting indicates a Bachelors degree with 0 years of industry experience.
Primary responsibilities include micro-architecture, RTL design, and performance/area/power trade-off analysis for cache and controller blocks.
Must-have technical skills and experience inferred from the posting.
Bachelors degree in a relevant field (e.g., Electrical Engineering, Computer Engineering, Computer Science) is specified. The posting indicates 0 years of industry experience. No alternative-equivalent phrasing or certifications were listed.
Company: Apple
Headquarters: Cupertino, California, United States
Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.
