ASIC Design and STA Engineer
Join the Networking Silicon physical design team as an STA engineer responsible for timing convergence and signoff for full chips and chiplets. The role involves clock planning, top-level floorplanning, timing integration of digital partitions and analog IP, and close collaboration with CAD, logic design, and DFT teams to deliver high-speed networking silicon.
Mid-level. The posting specifies 3+ years of relevant experience in physical design and STA.
Primary responsibilities include driving timing closure and collaborating across design disciplines to achieve signoff.
Must-have technical skills and experience.
B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering was specified.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
