ASIC Design and STA Engineer
Responsible for static timing analysis (STA) and timing convergence for high-speed networking ASICs (full-chip and chiplet) from early stages through signoff. Work includes top-level floorplanning, clock planning, timing integration of digital partitions and analog IP, and optimization of signoff CAD flows and methodologies.
Role is based in Bengaluru or Hyderabad and follows a hybrid work arrangement.
Mid-level β 3+ years of experience in physical design and STA.
Key duties include:
Must-have skills and experience:
B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
