ASIC Architect

Job Title

ASIC Architect

Role Summary

Design and optimize compute architectures for next-generation AI inference accelerators. Work on architectural exploration, performance modeling, and specification of compute blocks from concept through silicon.

This role partners closely with RTL, verification, physical design, and software teams to balance throughput, latency, power, and area for inference workloads.

Experience Level

Mid-level; typically requires 5+ years of experience in computer architecture, ASIC design, or closely related fields.

Responsibilities

Key responsibilities include architectural design, evaluation, and cross-functional integration.

• Design and analyze chip architectures optimized for AI/ML workloads with emphasis on throughput, latency, and power efficiency.
• Develop power and area estimation methods for early-stage architectural exploration.
• Create architectural specifications and interface definitions for compute blocks and subsystems.
• Run architectural experiments using cycle-accurate simulators and analytical models; perform performance modeling.
• Collaborate with RTL, verification, physical design, and software teams to ensure feasibility and optimize end-to-end design.
• Support integration and silicon bring-up by providing architectural guidance and resolving design challenges.

Requirements

Must-have technical skills and experience.

• 5+ years of experience in computer architecture, ASIC design, or related fields.
• Strong understanding of architecture fundamentals: pipelines, memory hierarchies, and interconnects.
• Experience with performance modeling and architectural simulation tools.
• Hands-on experience designing and optimizing floating-point datapaths or arithmetic‑intensive circuits; familiarity with advanced process nodes.
• Proficiency with Rust, C/C++, or Python for modeling and analysis.
• Strong analytical, problem-solving, and communication skills; proven ability to work in cross-functional teams.

Nice-to-have skills.

• Experience with AI/ML accelerator architectures and dataflow optimizations.
• RTL design and verification experience (Verilog/SystemVerilog).
• Familiarity with cycle-accurate simulation tools (gem5, SystemC, or custom simulators) and power/performance analysis methodologies.
• Knowledge of ASIC design flow, physical design constraints, tapeout, and silicon bring-up.
• Publications or presentations at architecture conferences (ISCA, MICRO, HPCA, etc.).

Education Requirements

PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related field (explicitly stated in the posting).

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.