Job Title
ASIC Architect
Role Summary
As an ASIC Architect on the architecture team, you will translate high-level architecture specifications into micro-architecture requirements, build and validate performance and power models, and guide PPA trade-offs for new features. You will profile workloads, identify bottlenecks, and collaborate with software teams to model application-level behavior at cluster scale.
Experience Level
Senior — 10+ years of relevant experience in performance analysis and modeling of GPUs, CPUs, or accelerator products.
Responsibilities
The role focuses on architecture-to-microarchitecture translation, modeling, and performance-driven feature definition.
- Translate high-level architecture specifications into micro-architecture feature requirements.
- Develop and validate performance and power models; bring up new features in models.
- Perform PPA (performance, power, area) trade-off analysis for architectural features.
- Profile workloads, identify performance bottlenecks, and benchmark against competitors.
- Collaborate with software teams for end-to-end application and cluster-level modeling.
- Identify opportunities for kernel-level hardware acceleration and micro-code optimizations.
Requirements
Must-have skills and experience:
- 10+ years in performance analysis and modeling for GPUs, CPUs, or accelerator products.
- Strong background in computer architecture and high-level architectural trade-offs.
- Experience creating performance models from scratch using Python or similar tools.
- Experience with profiling and diagnosing micro-code/kernel performance bottlenecks.
- Ability to extract insights on power efficiency and project performance for benchmarking.
- Effective collaboration with software teams for system-level evaluation.
Nice-to-have:
- Familiarity with ML workload profiling and neural network architectures.
- Experience with large-scale accelerator or cluster-level performance modeling.
Education Requirements
Master's or PhD in Electrical Engineering or Computer Engineering (as listed by the employer).
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.

Date Posted: 2026-07-28