ASIC 3D DRAM Architect
QualcommJob Title
ASIC 3D DRAM Architect
Role Summary
Design and architect 3D DRAM and near-memory compute solutions to maximize bandwidth, reduce latency, and improve power, thermal, area, and yield for data center, mobile, compute, and XR systems. Work within the Memory System/Technology team in Process & Package Solutions and collaborate with process & packaging, AI/compute architects, memory controller, SoC, and emulation teams.
Experience Level
Mid-level. Typical experience expectations vary by degree: PhD track ~4+ years, Master’s track ~5+ years, Bachelor’s track ~6+ years.
Responsibilities
Primary technical responsibilities include architecture, modeling, and system evaluation of 3D DRAM and near-memory compute.
- Develop and optimize 3D DRAM bank organization and near-memory computing architectures to maximize density and TOPS/mm² and TOPS/W.
- Develop and validate performance, power, and yield models for 3D DRAM as functions of bank configuration, TSVs, and power distribution.
- Design fabrics and data-distribution mechanisms to deliver high-bandwidth data from 3D DRAM arrays to near-memory compute units across workloads.
- Define power-distribution topologies to ensure robust DRAM operation in 3D stacks.
- Simulate and emulate system-level performance for AI, compute, and mobile workloads to evaluate architecture choices.
- Floorplan 3D DRAM chips and design memory array control structures considering 3D integration manufacturing constraints, testability, and repairability.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Experience in ASIC design, mixed-signal design, and performance modeling.
- Strong knowledge of memory architecture, bus protocols, and 2.5D/3D integration techniques.
- Proficiency with EDA tool flows and scripting/engineering tools; specifically MATLAB and Python.
- Ability to simulate/emulate system performance and to floorplan and design array control under 3D integration constraints.
- Strong problem-solving, communication skills, and ability to work independently and in cross-functional teams.
Nice-to-have / Preferred
- Experience in circuit and system design for dataflow modeling and optimization.
- Hands-on DRAM architecture performance assessment experience.
- Experience in memory circuit design (SRAM/DRAM/Flash/ROM/OPT).
- Familiarity with C/C++ and Verilog/Verilog-A/Verilog-AMS modeling.
- Familiarity with DRAM datasheets and I/O interfaces.
Education Requirements
Degree and experience combinations specified: Bachelor's degree in Science, Engineering, or related field with 6+ years of relevant ASIC/verification/validation/integration experience; OR Master’s degree in Science, Engineering, or related field with 5+ years; OR PhD in Science, Engineering, or related field with 4+ years. Preferred fields include Electrical Engineering, Computer Science, or related technical disciplines.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
