Architectural Modelling Engineer

Job Title

Architectural Modelling Engineer

Role Summary

Design and develop cycle-accurate and system-level hardware simulators used as the source of truth for architectural exploration and compiler optimization for a purpose-built analytics processor (APU).

Work on a cross-functional architectural team and collaborate with hardware (VLSI), software, and compiler engineers to influence chip architecture, tooling, and system-level performance.

Experience Level

Mid-level — typically requires 5+ years of professional experience developing in modern C++ and Python and working with system-level modeling or computer architecture concepts.

Responsibilities

Key day-to-day responsibilities include designing, implementing, and maintaining simulator infrastructure and tools, and informing architecture and compiler decisions.

• Develop new hardware simulators and evolve existing simulators.
• Collaborate with Architecture, VLSI, and Software teams on co-design initiatives.
• Provide analysis and insights that influence chip architecture, compiler optimizations, and system-level performance.
• Develop tools that support the chip development cycle and verification workflows.

Requirements

Must-have technical skills and experience.

• 5+ years developing production software in modern C++ and Python.
• Strong understanding of computer architecture and system-level modeling.
• Solid software engineering practices: design, testing, performance tuning, and maintainability.
• Interest and experience in SW–HW co-development and cross-discipline collaboration.

Nice-to-have:

• Experience developing hardware simulators.
• Experience in SW–HW co-development environments.
• Knowledge of SQL semantics and Parquet internals.

Education Requirements

BSc or higher in Computer Science, Mathematics, Physics, or Electrical Engineering, or equivalent practical experience.

About the Company

Company: Speedata

Speedata develops a purpose-built ASIC, the Analytics Processing Unit (APU), to accelerate analytics and AI data workloads (e.g., Apache Spark), improving query performance and reducing infrastructure TCO by executing analytics operations in silicon.