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Architect - Subsystem

Volantis Semiconductor
August 27, 2026
Full-time
Remote friendly (San Francisco, California, United States)
Worldwide
SoC Architecture Jobs, Level - Senior

Job Title

Architect - Subsystem

Role Summary

Own the architecture of a complete sub-block on the A-0 and A-1 systems and ensure it integrates into the broader chip and system. Collaborate with other architects, architecture leaders, microarchitects, implementation and verification teams to deliver a production-capable block.

Experience Level

Senior level. Specific years of experience are not stated, but the role requires demonstrated prior ownership of block-level architecture within larger chip or system projects.

Responsibilities

Primary responsibilities include end-to-end ownership, system integration, and technical collaboration.

  • Own architecture and delivery of a full sub-block within the A-0/A-1 systems.
  • Define interfaces and integration points with other subsystems and system-level architects.
  • Collaborate with microarchitects on implementation and with verification teams to validate the block.
  • Make architectural tradeoffs addressing performance, area, power, and scalability.
  • Coordinate with physical design and packaging teams as required for block implementation.

Requirements

Concise list of required and preferred qualifications.

  • Must-have: Hands-on experience owning and delivering the architecture of a block that was part of a larger chip or system.
  • Must-have: Understanding and hands-on experience in the design of AI accelerators.
  • Must-have: Experience working with microarchitects on implementation and with verification teams for the block.
  • Nice-to-have: Experience with the physical design process for the blocks you owned.
  • Nice-to-have: Experience with large die-area chips.
  • Nice-to-have: Experience with multi-die and multi-package chips and systems.

Education Requirements

Not specified.


About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.

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Date Posted: 2026-08-26