Architect, FPGA Design — AXI / UCIe / Protocol

Job Title

Architect, FPGA Design — AXI / UCIe / Protocol

Role Summary

Design and deliver Speed Adapter solutions that bridge multi-gigabit real-world I/O and reduced-speed DUTs on ZeBu emulation and HAPS prototyping platforms. Work across RTL, firmware, board-level hardware, and integration with IP and emulation teams to enable system-level validation of advanced protocols.

Experience Level

Senior — 12+ years of relevant experience.

Responsibilities

You will design, implement, and support FPGA-based protocol adapters and system-level validation flows.

• Design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI protocols.
• Implement protocol logic and speed-adaptation functionality on FPGA platforms to translate between multi-gigabit interfaces and reduced-speed DUTs.
• Develop and debug RTL, firmware, and system-level components from transceiver configuration to protocol state machines and host integration.
• Collaborate with IP teams, emulation and prototyping engineers, and customers to deliver integrated validation solutions.
• Build reference designs, example flows, and integration documentation for customer deployment.
• Support customer escalations and perform root-cause analysis across hardware, firmware, and protocol layers.
• Contribute to product roadmap and feature definition for next-generation Speed Adapter products.

Requirements

Must-have technical skills, plus some desirable experience.

• Extensive hands-on experience with protocol implementation or validation — deep experience with at least two: UCIe, PCIe (Gen4+), CXL (2.0+), or AXI.
• Strong RTL development skills and proven experience designing, debugging, and deploying logic on FPGA platforms in production or customer-facing environments.
• Experience with system-level validation, emulation, or prototyping environments and cross-domain bring-up/debug.
• Solid understanding of high-speed serial interfaces: transceiver configuration, link training, and physical-layer bring-up.
• Demonstrated ability to debug across RTL, firmware, and board-level hardware using waveform viewers, logic analyzers, protocol analyzers, and embedded debuggers.
• Ability to work directly with customers in lab environments to diagnose and resolve system-level failures.
• Nice-to-have: experience with ZeBu, HAPS, Veloce, Palladium, In-Circuit Emulation or Direct-ICE workflows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field; or equivalent hands-on experience in digital design and FPGA-based systems.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.