Architect, FPGA Design (AXI, UCIe, Protocol)

Job Title

Architect, FPGA Design (AXI, UCIe, Protocol)

Role Summary

Senior engineering role on the Speed Adapter team within Hardware-Assisted Verification (TPG-HAV). Design and deliver FPGA-based adapter solutions that bridge multi-gigabit real-world interfaces and reduced-speed DUTs on emulation and prototyping platforms.

The team integrates protocol logic, transceiver configuration, firmware, and host integration to enable system-level validation for customers using ZeBu, HAPS and related platforms.

Experience Level

Senior — 12+ years of relevant experience.

Responsibilities

Key responsibilities include:

• Design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI to connect real devices with ZeBu and HAPS platforms.
• Implement protocol logic and speed adaptation on FPGA platforms, managing translation between multi-gigabit interfaces and reduced-speed DUTs.
• Develop and debug RTL, firmware, and system-level components across the full adapter stack, from transceiver setup to protocol state machines and host integration.
• Collaborate with IP, emulation, and prototyping teams to deliver integrated, customer-deployable validation solutions and reference designs.
• Create example flows, integration documentation, and reference designs to simplify customer bring-up.
• Support customer escalations with root-cause analysis across hardware, firmware, and protocol layers.
• Contribute to product roadmap and feature definition for next-generation Speed Adapter capabilities.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Deep hands-on implementation or validation experience with at least two of: UCIe, PCIe (Gen4+), CXL (2.0+), AXI.
• Strong RTL development skills and experience deploying logic on FPGA platforms in production or customer-facing environments.
• Experience with system-level validation, emulation, or prototyping workflows and working across the hardware/software boundary to bring up complex systems.
• Solid understanding of high-speed serial interfaces, including transceiver configuration, link training, and physical-layer bring-up.
• Proven ability to debug across RTL, firmware, and board-level hardware using waveform viewers, logic analyzers, protocol analyzers, and embedded debuggers.
• Ability to produce maintainable RTL, consider FPGA resource and timing tradeoffs, and present technical tradeoffs to architects and customers.

Nice-to-have:

• Experience with ZeBu, HAPS, Veloce, Palladium, or similar emulation/prototyping platforms.
• Familiarity with In-Circuit Emulation, Direct-ICE workflows, or customer lab bring-up processes.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience in digital design and FPGA-based systems. Equivalent practical experience accepted.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.