Applications Engineering, Staff Engineer - PrimeTime

Job Title

Applications Engineering, Staff Engineer - PrimeTime

Role Summary

Senior applications engineer focused on Synopsys PrimeTime static timing analysis (STA). The role supports pre-sales evaluations, customer training, and post-sales tape-out troubleshooting to accelerate timing closure and increase tool adoption.

Work directly with customer design teams, field sales, and R&D to resolve timing issues, demonstrate performance advantages, and translate field challenges into product improvements.

Experience Level

Senior - typically 7+ years of hands-on experience in ASIC/SoC design, timing analysis, or related fields.

Responsibilities

Provide technical leadership and hands-on customer support across the full design flow to ensure successful timing closure and PrimeTime adoption.

• Drive PrimeTime adoption in pre-sales evaluations and post-sales deployments, including benchmarking and proof-of-concept runs.
• Deliver hands-on customer training on STA workflows, timing closure techniques, process variation analysis, and signal integrity debugging.
• Provide tape-out support: troubleshoot timing violations, setup/hold issues, and corner-case scenarios in production designs.
• Collaborate with R&D to report field issues, communicate customer requirements, and influence product enhancements.
• Work with sales and field teams to articulate technical advantages and support technical win strategies.
• Develop and maintain TCL-based automation and methodologies to improve customer productivity and timing closure efficiency.
• Interface with synthesis, physical design, extraction, and ECO processes to ensure seamless PrimeTime integration.

Requirements

Must-have technical skills and experience for effective customer-facing STA support.

• Deep, hands-on experience with Synopsys PrimeTime running STA, reading reports, and debugging violations in real designs.
• Strong understanding of timing corners, process variation, OCV/AOCV, statistical STA, and signal integrity impacts on timing.
• Familiarity with the digital design flow: synthesis, place & route, parasitic extraction, and ECO methodologies.
• Proficient TCL scripting for automation, flow customization, and productivity improvements.
• Proven customer-facing communication skills; able to explain complex technical issues to engineers and management.
• Willingness to travel to customer sites as required for training, support, and technical engagements.
• Nice-to-have: prior experience running competitive benchmarks and producing measurable performance comparisons.

Education Requirements

Bachelor's degree in Electrical Engineering (or equivalent) with 7+ years of relevant experience, or a Master's degree with 7+ years of relevant experience. Equivalent practical experience in ASIC/SoC design and timing analysis is acceptable.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.