Applications Engineering, Sr Staff Engineer (Physical Verification)
SynopsysJob Title
Applications Engineering, Sr Staff Engineer (Physical Verification)
Role Summary
Senior engineer on the Physical Verification Applications Engineering team responsible for driving signoff verification, methodology development, and automation for advanced-node semiconductor designs. The role partners with customers, foundries, and internal product and engineering teams to resolve complex signoff challenges and improve verification predictability.
Experience Level
Senior - typically 8+ years for a B.Tech or 6+ years for an M.Tech in relevant VLSI roles (see Education Requirements for details).
Responsibilities
Lead technical activities to achieve reliable signoff and scalable verification flows for advanced process-node projects.
- Lead Physical Verification signoff for strategic customers and large-scale SoC/custom projects.
- Drive closure of DRC, LVS, ERC, PERC, Density, Antenna, and Reliability verification issues.
- Develop and deploy scalable PV methodologies, automation frameworks, and verification flows.
- Collaborate with Physical Design, Custom Design, Technology/Foundry, CAD, Product Engineering, and R&D to resolve signoff issues.
- Analyze technical risks, identify verification bottlenecks, and mitigate schedule impacts to tapeout.
- Provide technical leadership and mentor engineering teams; promote verification best practices.
- Capture customer feedback and drive improvements into Synopsys product and methodology roadmaps.
Requirements
Must-have technical skills and experience for immediate contribution to signoff and methodology efforts.
- Strong expertise in Physical Verification signoff flows including DRC, LVS, ERC, PERC, Density, Antenna, and Reliability verification.
- Hands-on experience with industry PV tools such as Synopsys IC Validator, Siemens Calibre, Cadence Pegasus, or equivalent platforms.
- Deep understanding of advanced semiconductor technologies (7nm, 5nm, 3nm and beyond) and advanced process-node signoff methodologies.
- Strong knowledge of semiconductor manufacturing, device physics, physical layout design, and Design-for-Manufacturing (DFM).
- Proven track record debugging complex PV violations and driving signoff closure on large projects.
- Strong scripting and automation skills (Python, Perl, Tcl, Shell, or similar) and experience building reusable methodologies.
- Experience collaborating with cross-functional teams and influencing technical direction without direct authority.
- Nice-to-have: exposure to cloud computing, distributed verification environments, or large-scale compute infrastructures.
Education Requirements
B.Tech with 8+ years or M.Tech with 6+ years of experience in Physical Verification, Physical Design, or related VLSI domains.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
